CY8C36_10 CYPRESS [Cypress Semiconductor], CY8C36_10 Datasheet - Page 24

• Manufacturer Part Number: CY8C36_10
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in
Document Number: 001-53413 Rev. *I
The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
Bus clock 16-bit divider uses the system clock to generate the
system's bus clock used for data transfers. Bus clock is the
source clock for the CPU clock divider.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the Universal Digital Blocks (UDBs) and fixed function
timer/counter/PWMs can also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADC and mixers.
The analog clock dividers include skew control to ensure that
critical analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
Figure 2-6
on page 10.
Vddio1
Vddio2
Vssd
0.1 µF
0.1µF
I/O Supply
I/O Supply
Domain
Digital
PRELIMINARY
Figure 6-4. PSoC Power System
1 µF
Regulators
Digital
0.1 µF
Vddd
Vddd
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled Vdda, Vddd, and Vddio×, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(Vccd) and analog (Vcca) supplies for the internal core logic. The
output pins of the regulators (Vccd and Vcca) and the Vddio pins
must have capacitors connected as shown in
two Vccd pins must be shorted together, with as short a trace as
possible, and connected to a 1-µF ±10% ×5R capacitor. The
power system also contains a sleep regulator, an I
and a hibernate regulator.
PSoC
0.1 µF
I/O Supply
Regulator
Regulator
Regulator
Analog
Regulator
Hibernate
Domain
Analog
Sleep
I2C
I/O Supply
®
3: CY8C36 Family Datasheet
0.1 µF
Vddio0
Vdda
Vcca
Vssa
Vddio3
Vddio0
1 µF
0.1 µF
Vdda
0.1µF
.
Figure
2
C regulator,
Page 24 of 112
6-4. The
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