CY8C36_10 CYPRESS [Cypress Semiconductor], CY8C36_10 Datasheet - Page 61

• Manufacturer Part Number: CY8C36_10
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 11-3. AC Specifications
Document Number: 001-53413 Rev. *I
Note
F
F
Svdd
T
T
T
T
28. Based on device characterization (Not production tested).
STARTUP
SLEEP
IO_INIT
CPU
BUSCLK
HIBERNATE
Parameter
CPU frequency
Bus frequency
V
Time from V
≥ IPOR to I/O ports set to their reset
states
Time from V
≥ PRES to CPU executing code at
reset vector
Wakeup from sleep mode –
Application of non–LVD interrupt to
beginning of execution of next CPU
instruction
Wakeup from hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
DD
ramp rate
Description
DDD
DDD
[28]
/V
/V
DDA
DDA
1.71 V
/V
/V
5.5 V
3.3 V
0.5 V
0 V
CCD
CCD
DC
PRELIMINARY
/V
/V
CCA
CCA
Figure 11-1. F
Valid Operating Region with SMP
1.71 V ≤ V
1.71 V ≤ V
V
V
boot mode (48 MHz typ.)
V
V
IMO boot mode (12 MHz typ.)
CCA
DDA
CCA
DDA
Valid Operating Region
/V
/V
/V
/V
CPU Frequency
1 MHz
DDA
DDD
CCD
DDD
DDD
DDD
Conditions
, no PLL used, fast IMO
, no PLL used, slow
= regulated from
= regulated from
CPU
≤ 5.5 V
≤ 5.5 V
PSoC
vs. V
DD
10 MHz
®
3: CY8C36 Family Datasheet
67 MHz
Min
DC
DC
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
Max
100
67
67
10
33
66
15
1
Page 61 of 112
Units
MHz
MHz
V/ns
µs
µs
µs
µs
µs
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