ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 116

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 12337
Product data
16.1.5 DcInterruptEnable register (R/W: C3H/C2H)
Table 115: DcHardwareConfiguration register: bit description
This command is used to individually enable or disable interrupts from all endpoints,
as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT,
suspend, resume, reset). A bus reset will not change any of the programmed bit
values.
The command accesses the DcInterruptEnable register, which consists of 4 bytes.
The bit allocation is given in
Bit
15
14
13
12
11 to 8
7
6
5
4
3
2
1
0
Symbol
-
EXTPUL
NOLAZY
CLKRUN
CKDIV[3:0]
DAKOLY
DRQPOL
DAKPOL
-
WKUPCS
-
INTLVL
INTPOL
Rev. 03 — 06 January 2004
Description
reserved
Logic 1 indicates that an external 1.5 k pull-up resistor is used
on pin OTG_DP1 (in the device mode) and that SoftConnect is
not used. Bus reset value: unchanged.
Logic 1 disables output on pin CLKOUT of the LazyClock
frequency (115 kHz
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
of the DcMode register. Bus reset value: unchanged.
Logic 1 indicates that the internal clocks are always running,
even during the ‘suspend’ state. Logic 0 switches off the internal
oscillator and PLL, when they are not needed. During the
‘suspend’ state, this bit must be made logic 0 to meet the
suspend current requirements. The clock is stopped after a
delay of approximately 2 ms, following the setting of
bit GOSUSP of the DcMode register. Bus reset value:
unchanged.
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by
3 MHz to 48 MHz (N = 0 to 15), with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
Logic 1 selects the DACK-only DMA mode. Logic 0 selects the
8237 compatible DMA mode. Bus reset value: unchanged.
Selects the DREQ2 pin signal polarity (0 = active LOW;
1 = active HIGH). Bus reset value: unchanged.
Selects the DACK2 pin signal polarity (0 = active LOW;
1 = active HIGH). Bus reset value: unchanged.
reserved
Logic 1 enables remote wake-up using a LOW level on input CS.
Bus reset value: unchanged.
reserved
Selects the interrupt signalling mode on output (0 = level;
1 = pulsed). In the pulsed mode, an interrupt produces 166 ns
pulse. Bus reset value: unchanged.
Selects the INT2 signal polarity (0 = active LOW; 1 = active
HIGH). Bus reset value: unchanged.
Table
116.
48
N
50 %) during the ‘suspend’ state. Logic 0
+
1
Single-chip USB OTG controller
. The clock frequency range is
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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