ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 33

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 12337
Product data
11.3.1 B-device initiating SRP
11.3.2 A-device responding to SRP
11.3 Session Request Protocol (SRP)
communicates with the A-device as long as it wishes. When the B-device finishes
communicating with the A-device, both the devices finally go into the idle state. See
Figure 18
As a dual-role device, the ISP1362 can initiate and respond to SRP. The B-device
initiates SRP by data line pulsing followed by V
either data line pulsing or V
The ISP1362 can initiate SRP by performing the following steps:
The B-device must complete both data line pulsing and V
The A-device must be able to respond to one of the two SRP events: data line pulsing
or V
mechanism to disable or enable the SRP detection. This is useful for some
applications under certain cases. For example, if the A-device battery is low, it may
not want to turn on its V
the SRP detection function.
When the data line SRP detection is used, the ISP1362 can detect either the
DP pulsing or the DM pulsing. This means a peripheral-only device can initiate data
line pulsing SRP through DP (full-speed) or DM (low-speed). A dual-role device will
always initiate data line pulsing SRP through DP because it is a full-speed device.
•
•
•
1. Detect initial conditions [read ID_REG, B_SESS_END and SE0_2MS (bits 0,
2. Start data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 1].
3. Wait for 5 ms to 10 ms.
4. Stop data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 0].
5. Start V
6. Wait for 10 ms to 20 ms.
7. Stop V
8. Discharge V
Steps to enable the SRP detection by V
Steps to enable the SRP detection by data line pulsing:
Steps to disable the SRP detection:
– Set A_SEL_SRP (bit 9) of the OtgControl register to logic 0.
– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
– Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1.
– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 0.
2 and 9) of the OtgStatus register].
OtgControl register], optional.
BUS
pulsing. The ISP1362 allows you to choose which SRP to support and has a
and
BUS
BUS
Figure
pulsing [set CHRG_V
pulsing [set CHRG_V
BUS
Rev. 03 — 06 January 2004
for about 30 ms [by using DISCHRG_V
19.
BUS
BUS
by detecting SRP. In this case, it may choose to disable
pulsing.
BUS
BUS
(bit 1) of the OtgControl register to logic 0].
(bit 1) of the OtgControl register to logic 1].
BUS
pulsing:
BUS
Single-chip USB OTG controller
pulsing. The A-device can detect
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
BUS
BUS
pulsing within 100 ms.
(bit 2) of the
ISP1362
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