LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 140

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.36
7.37
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
PS_ON Logic
The nPS_ON is a function of nSLP_S3 and nCPU_PRESENT according to the truth table below.
The nCPU_PRESENT is the signal from the processor that tells the system whether or not a processor
has been plugged in. The nCPU_PRESENT will be pulled to VTR through a 30uA resistor inside the chip.
The nPS_ON is used as the power down signal for the power supply. Since nPS_ON is an open drain
output, it may need to be pulled through a 1kohm resistor to V_5P0_STBY external to the chip if such a
pull-up is not provided on the power supply. The power supply turn-on circuit behaves according to the
table below.
See Table 13.3 for nPS_ON timing.
PWRGD_3V Logic
The PWRGD_3V is an AND function of PWRGD_PS and nFPRST.
The inputs, PWRGD_PS and nFPRST have hysteresis and are internally pulled to VTR through a 30uA
resistor. The nFPRST is debounced internally.
nFPRST has internal debounce circuitry that is valid on both edges for at least 16ms before the output is
changed. The 32.768kHz is used to meet the timing requirement. See Figure 7.14 for nFPRST debounce
timing.
nPS_ON
nCPU_PRESENT
nSLP_S3
nFPRST
PWRGD_PS
PWRGD_3V
NCPU_PRESENT
NAME
NAME
Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins
Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins
0
0
1
1
OD8
ISPU_400
I
ISPU_400
ISPU_400
O8
Table 7.38 - nPS_ON Truth Table
INPUTS
BUFFER
BUFFER
DATASHEET
NSLP_S3
POWER
VTR
VTR
VTR
Page 140
WELL
0
1
0
1
POWER
VTR
VTR
VTR
WELL
Reset Input from Front Panel
Power Good Input from
Power Supply
Power Good Output
Power Supply Turn-ON Open
Drain Output
CPU Present Input from
Processor
S3 Power State Input from
South Bridge
DESCRIPTION
DESCRIPTION
OUTPUT
nPS_ON
Hi-Z
Hi-Z
Hi-Z
0
SMSC LPC47M172