LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 40

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
BIT 3 READ DATA TOGGLE
BIT 4 WRITE DATA TOGGLE
BIT 5 DRIVE SELECT 0
BIT 6 RESERVED
BIT 7 RESERVED
PS/2 Model 30 Mode
BIT 0 nDRIVE SELECT 2
BIT 1 nDRIVE SELECT 3
BIT 2 WRITE GATE
BIT 3 READ DATA
BIT 4 WRITE DATA
BIT 5 nDRIVE SELECT 0
BIT 6 nDRIVE SELECT 1
BIT 7 nDRV2
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Every inactive edge of the RDATA input causes this bit to change state.
Every inactive edge of the WDATA input causes this bit to change state.
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a
hardware reset and it is unaffected by a software reset.
Always read as a logic “1”.
Always read as a logic “1”
The DS2 disk interface is not supported.
The DS3 disk interface is not supported.
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of
WGATE and is cleared by the read of the DIR register.
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of
RDATA and is cleared by the read of the DIR register.
Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of
WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.
Active low status of the DS0 disk interface output.
Active low status of the DS1 disk interface output.
Active low status of the DRV2 disk interface input. Note: This function is not supported.
RESET
COND.
nDRV2
N/A
7
nDS1
6
1
DATASHEET
nDS0
5
1
WDATA
Page 40
F/F
4
0
RDATA
F/F
3
0
WGATE
F/F
2
0
nDS3
1
1
nDS2
0
1
SMSC LPC47M172