LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 163

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47M172
PME_STS3
Default = 0x00
PME_STS2
Default = 0x00
on VTR POR
on VTR POR
NAME
REG OFFSET
(Type)
(R/W)
(R/W)
0x08
0x09
PME Wake Status Register 3
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_En bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] GP23
Bits[7:4] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME Wake Status Register 2
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_En bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
DATASHEET
Page 163
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Datasheet