LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 155

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47M172
Force Disk Change
Default = 0x01 on
VCC POR
Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
INT_GEN1
Default = 0xFF
on VCC POR and
HARD RESET
NAME
REG OFFSET
(Type)
(R/W)
(R/W)
0x1A
0x18
0x19
0x1B
(R)
(R)
DATASHEET
Force Disk Change
Bit[0] Force Disk Change for FDC0
0=Inactive
1=Active
Bit[1] Reserved
Force Change 0 can be written to 1 but is not clearable by
software. Force Change 0 is cleared on nSTEP and
nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force
Change 0) OR nDSKCHG
Setting the Force Disk Change bit active ‘1’ forces the
FDD nDSKCHG input active.
Bit[7:2] Reserved
Floppy Data Rate Select Shadow
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
UART FIFO Control Shadow 1
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Interrupt Generating Register 1 (Note 2)
0=Corresponding Interrupt frame driven low in the SER
IRQ stream. This must be enabled through the INT_G
Configuration Register.
Bit[0] Reserved
Bit[1] nINT1
Bit[2] nINT2
Bit[3] nINT3
Bit[4] nINT4
Bit[5] nINT5
Bit[6] nINT6
Bit[7] nINT7
Note:
Page 155
To enable/disable this register see Logical
Device A (0xF1)
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Datasheet