LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 168

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
INT_GEN1
Default = 0xFF
on VCC POR and
HARD RESET
INT_GEN2
Default = 0xFF
on VCC POR and
HARD RESET
N/A
UART2 FIFO
Control Shadow
N/A
GP10
Default = 0x01
on VTR POR
NAME
REG OFFSET
0x1D-0x1F
(Type)
(R/W)
(R/W)
(R/W)
0x1C
0x1D
0x1B
0x1F
0x20
(R)
(R)
(R)
Interrupt Generating Register 1 (Note 2)
0=Corresponding Interrupt frame driven low in the SER IRQ stream. This
must be enabled through the INT_G Configuration Register.
Bit[0] Reserved
Bit[1] nINT1
Bit[2] nINT2
Bit[3] nINT3
Bit[4] nINT4
Bit[5] nINT5
Bit[6] nINT6
Bit[7] nINT7
Note:
Interrupt Generating Register 2 (Note 2)
0=Corresponding Interrupt frame driven low in the SER IRQ stream. This
must be enabled through the INT_G Configuration Register.
Bit[0] nINT8
Bit[1] nINT9
Bit[2] nINT10
Bit[3] nINT11
Bit[4] nINT12
Bit[5] nINT13
Bit[6] nINT14
Bit[7] nINT15
Note:
Bits[7:0] Reserved – reads return 0
UART FIFO Control Shadow 2
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bits[7:0] Reserved – reads return 0
General Purpose I/O bit 1.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DATASHEET
To enable/disable this register see Logical Device A (0xF1)
To enable/disable this register see Logical Device A (0xF1)
Page 168
DESCRIPTION
SMSC LPC47M172