LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 183

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47M172
I/O Base Address
(see Device Base I/O
Address Table)
Default = 0x00
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
Interrupt Select
Defaults :
0x70 = 0x00 or 0x06
(Note)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
0x72 = 0x00,
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
DMA Channel Select
Default = 0x02 or 0x04
(Note)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
32-Bit Memory Space
Configuration
Logical Device
Logical Device
Configuration
Reserved
LOGICAL DEVICE
REGISTER
(0xA9-0xDF)
(0xE0-0xFE)
(0x60-0x6F)
(0x76-0xA8)
(0x70,0x72)
(0x71,0x73)
(0x74,0x75)
0x60,2,... =
0x61,3,... =
ADDRESS
addr[15:8]
addr[7:0]
DATASHEET
0xFF
Page 183
Registers 0x60 and 0x61 set the base address
for the device. If more than one base address
is required, the second base address is set by
registers 0x62 and 0x63.
Refer to Table 11.7 and Table 11.8 for the
number of base address registers used by
each device.
Unused registers will ignore writes and return
zero when read.
Note:
device is not within the Base I/O range as
shown in the Logical Device I/O map, then
read or write is not valid and is ignored.
0x70 is implemented for each logical device.
Refer to Interrupt Configuration Register
description. Only the keyboard controller uses
Interrupt Select register 0x72. Unused register
(0x72) will ignore writes and return zero when
read. Interrupts default to edge high (ISA
compatible).
Refer to Table 11.5
Note:
Interrupt Select register for logical device 0 is
0x06.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Only 0x74 is implemented for FDC and Parallel
port. 0x75 is not implemented and ignores
writes and returns zero when read. Refer to
Table 11.6.
Note:
Channel Select register for logical device 0
(FDD) is 0x02 and for logical device 4 (UART)
is 0x04.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved – Vendor Defined (see SMSC
defined Logical Device Configuration
Registers).
Reserved
If the I/O Base Addr of the logical
The default value of the Primary
The default value of the DMA
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Datasheet