LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 167

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47M172
MSC_STS
Default = 0x00
Force Disk Change
Default = 0x01 on
VCC POR
Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
on VTR POR
NAME
REG OFFSET
(Type)
(R/W)
(R/W)
0x1A
0x17
0x18
0x19
(R)
(R)
Miscellaneous Status Register
Bits[1:0] can be cleared by writing a 1 to their position (writing a 0 has no
effect).
Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an
edge occurs on the GP21 pin.
Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an
edge occurs on the GP22 pin.
Bit[7:2] Reserved. This bit always returns zero.
Force Disk Change
Bit[0] Force Disk Change for FDC0
0=Inactive
1=Active
Bit[1] Reserved
Force Change 0 can be written to 1 but is not clearable by software. Force
Change 0 is cleared on nSTEP and nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR
nDSKCHG
Setting the Force Disk Change bit active ‘1’ forces the FDD nDSKCHG input
active.
Bit[7:2] Reserved
Floppy Data Rate Select Shadow
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
UART FIFO Control Shadow 1
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
DATASHEET
Page 167
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Datasheet