LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 192

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note 1:
Note:
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
PP Mode Register 2
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
TEST10
Default = 0x08
on VCC POR,
VTR POR and
HARD RESET
Serial Port 1 Mode
Register
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
To properly share and IRQ,
1. Configure UART1 (or UART2) to use the desired IRQ.
2. Configure UART2 (or UART1) to use No IRQ selected.
3. Set the share IRQ bit.
If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART
IRQs will assert when either UART generates an interrupt.
NAME
NAME
Table 11.12 - Serial Port 1 Logical Device Configuration Registers
REG INDEX
REG INDEX
0xF1 R/W
0xF8 R/W
0xF0 R/W
DATASHEET
Bits[3:0] Reserved. Set to zero
Bit [4] TIMEOUT_SELECT
= 0 TMOUT (EPP Status Reg.) cleared on write of ‘1’ to
TMOUT.
= 1 TMOUT cleared on trailing edge of read of EPP
Status Reg.
Bits[7:5] Reserved. Set to zero.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired results.
Bit[0] MIDI Mode
= 0
= 1
Bit[1] High Speed
= 0
= 1
Bit[6:2] Reserved, set to zero
Bit[7] Share IRQ
=0 UARTS use different IRQs
=1 UARTS share a common IRQ
See Note 1 below.
Page 192
MIDI support disabled (default)
MIDI support enabled
High Speed Disabled(default)
High Speed Enabled
DEFINITION
DEFINITION
SMSC LPC47M172