LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 7

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Chapter 13
Chapter 14
Chapter 15
Chapter 16
List Of Figures
Figure 2.1 - LPC47M172 Pin Layout ............................................................................................................................12
Figure 4.1 - LPC47M172 Block Diagram......................................................................................................................28
Figure 7.1 - NKBDRST Circuit....................................................................................................................................120
Figure 7.2 - Keyboard Latch.......................................................................................................................................121
Figure 7.3 - Mouse Latch ...........................................................................................................................................121
Figure 7.4 - GPIO Function Illustration.......................................................................................................................126
Figure 7.5 - Fan Tachometer Input and Clock Source ...............................................................................................130
Figure 7.6 - NHD_LED Circuit ....................................................................................................................................132
Figure 7.7 - YLW_LED/GRN_LED Circuit ..................................................................................................................133
Figure 7.8 - REF5V Circuit .........................................................................................................................................134
Figure 7.9 - REF5V_STBY.........................................................................................................................................135
Figure 7.10 - VGA DDC Voltage Translation Circuit...................................................................................................138
Figure 7.11 - SMBUS Isolation Circuit........................................................................................................................139
Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation ......................................................................................141
Figure 7.13 - PWRGD_3V Circuit in LPC47M172 ......................................................................................................141
Figure 7.14 - NFPRST Timing....................................................................................................................................142
Figure 7.15 - SCK_BJT_Gate Circuit .........................................................................................................................143
Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................144
Figure 7.17 - Latched Backfeed Cut Power Up Sequence.........................................................................................145
Figure 7.18 - Latched Backfeed Cut Sequence 1 ......................................................................................................145
Figure 7.19 - Latched Backfeed Cut Sequence 2 ......................................................................................................146
Figure 7.20 - Latched Backfeed Cut Flowchart ..........................................................................................................147
Figure 7.21 - CNR Circuit ...........................................................................................................................................149
Figure 13.1 - Power-Up Timing ..................................................................................................................................203
Figure 13.2 - Input Clock Timing ................................................................................................................................204
Figure 13.3 - PCI Clock Timing ..................................................................................................................................204
Figure 13.4 - Reset Timing.........................................................................................................................................204
Figure 13.5 - Output Timing Measurement Conditions, LPC Signals .........................................................................205
Figure 13.6 - Input Timing Measurement Conditions, LPC Signals............................................................................205
Figure 13.7 - I/O Write................................................................................................................................................205
Figure 13.8 - I/O Read ...............................................................................................................................................206
Figure 13.9 - DMA Request Assertion through NLDRQ .............................................................................................206
Figure 13.10 - DMA Write (First Byte) ........................................................................................................................206
Figure 13.11 - DMA Read (First Byte)........................................................................................................................206
Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) ...........................................................................................207
Figure 13.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................208
Figure 13.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................209
Figure 13.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................210
Figure 13.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................210
Figure 13.17 - Parallel Port FIFO Timing ...................................................................................................................212
Figure 13.18 - ECP Parallel Port Forward Timing ......................................................................................................213
Figure 13.19 - ECP Parallel Port Reverse Timing ......................................................................................................214
Figure 13.20 - Setup and Hold Time ..........................................................................................................................215
Figure 13.21 - Serial Port Data...................................................................................................................................215
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
13.1
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
ECP Parallel Port Timing ......................................................................................................................211
Timing Diagrams ................................................................................................................202
Package Outline ................................................................................................................. 223
Board Test Mode................................................................................................................224
Reference Documents........................................................................................................ 226
Parallel Port FIFO (Mode 101).......................................................................................................211
ECP Parallel Port Timing ...............................................................................................................211
Forward-Idle ..................................................................................................................................211
Forward Data Transfer Phase .......................................................................................................211
Reverse-Idle Phase .......................................................................................................................211
Reverse Data Transfer Phase .......................................................................................................211
Output Drivers ...............................................................................................................................212
DATASHEET
Page 7
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M172
Datasheet