AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 138

• Manufacturer Part Number: AT89C51CC03U-S3SIM
• Description: Enhanced 8-bit MCU with CAN Controller and Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Registers
Serial Peripheral Control
Register (SPCON)
138
AT89C51CC03
Figure 66. SPI Interrupt Requests Generation
Three registers in the SPI module provide control, status and data storage functions.
These registers are describe in the following paragraphs.
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Table 92 describes this register and explains the use of each bit
Table 92. SPCON Register
SPCON - Serial Peripheral Control Register (0D4H)
Bit Number
SPR2
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
7
7
6
5
4
SPEN
6
Bit Mnemonic
MODFIE
SPTEIE
MODF
SPTE
SPIF
SSDIS
SPEN
MSTR
SPR2
SSDIS
5
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and
SPR0 for detail).
Serial Peripheral Enable
Cleared to disable the SPI interface (internal reset of the SPI).
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
MSTR
4
CPOL
3
.
CPHA
CPU Interrupt Request
2
SPI
4182I–CAN–06/05
SPR1
1
SPR0
0