AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 43

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AT89C51CC03U-S3SIM

Manufacturer Part Number
AT89C51CC03U-S3SIM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Figure 22. External Code Fetch Waveforms
Flash Memory
Architecture
Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode)
4182I–CAN–06/05
Extra Row (128 Bytes)
Hardware Security (1 byte)
Column Latches (128 Bytes)
CPU Clock
PSEN#
ALE
P0
P2
D7:0
PCH
AT89C51CC03 features two on-chip Flash memories:
The FM0 can be program by both parallel programming and Serial In-System Program-
ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP
mode is detailed in the "In-System Programming" section.
All Read/Write access operations on Flash Memory by user application are managed by
a set of API described in the "In-System Programming" section.
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Figure
23 and Figure 24 show the Flash memory configuration with ENBOOT=1 and
ENBOOT=0.
FFFFh
F800h
0000h
Flash memory FM0:
containing 64K Bytes of program memory (user space) organized into 128 byte
pages,
Flash memory FM1:
2K Bytes for boot loader and Application Programming Interfaces (API).
PCL
64K Bytes
FM0
PCH
Memory space not accessible
D7:0
FM1 mapped between FFFFh and
F800h when bit ENBOOT is set in
AUXR1 register
PCL
Flash memory
boot space
2K Bytes
FM1
PCH
D7:0
FFFFh
F800h
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