AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 73

• Manufacturer Part Number: AT89C51CC03U-S3SIM
• Description: Enhanced 8-bit MCU with CAN Controller and Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Interrupt
Registers
4182I–CAN–06/05
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This
flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer
interrupt routine. Interrupts are enabled by setting
interrupts are globally enabled by setting EA bit in IEN0 register.
Figure 39. Timer Interrupt System
Table 30. TCON Register
TCON (S:88h)
Timer/Counter Control Register
Reset Value = 0000 0000b
Number
TF1
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
TR1
TF1
TR1
TF0
TR0
Bit
IE1
IE0
IT1
IT0
6
TCON.5
TCON.7
TF0
TF1
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
Timer 1 Run Control Bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
Timer 0 Run Control Bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1).
Set by hardware when external interrupt is detected on INT1# pin.
Interrupt 1 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0).
Set by hardware when external interrupt is detected on INT0# pin.
Interrupt 0 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) for external interrupt 0.
TF0
5
TR0
4
IEN0.1
IEN0.3
ET0
ET1
IE1
3
ETx
Timer 0
Interrupt Request
Timer 1
Interrupt Request
bit in IEN0 register. This assumes
IT1
2
IE0
1
IT0
0
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