AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 140

• Manufacturer Part Number: AT89C51CC03U-S3SIM
• Description: Enhanced 8-bit MCU with CAN Controller and Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Serial Peripheral DATa Register
(SPDAT)
140
AT89C51CC03
Reset Value = 00X0 XXXXb
Not Bit addressable
The Serial Peripheral Data Register (Table 94) is a read/write buffer for the
receive/transmit data register.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
A Write of the SPDAT loads the data to be transmited in the transmit register.
Table 94. SPDAT Register
SPDAT - Serial Peripheral Data Register (0D6H)
Reset Value = Indeterminate
Number
Bit
R7
7
4
3
2
1
0
Mnemonic Description
MODFIE
UARTM
SPTEIE
MODF
SPTE
Bit
R6
6
Mode Fault
- Set by hardware to indicate that the SS pin is in inappropriate logic level (in both
master and slave modes).
- Cleared by hardware when reading SPSCR
When MODF error occurred:
- In slave mode: SPI interface ignores all transmitted data while SS remains high.
A new transmission is perform as soon as SS returns low.
- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN
bit in SPCON register).
Serial Peripheral Transmit register Empty
- Set by hardware when transmit register is empty (if needed, SPDAT can be
loaded with another data).
- Cleared by hardware when transmit register is full (no more data should be
loaded in SPDAT).
Serial Peripheral UART mode
Set and cleared by software:
- Clear: Normal mode, data are transmitted MSB first (default)
- Set: UART mode, data are transmitted LSB first.
Interrupt Enable for SPTE
Set and cleared by software:
- Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is
generated).
- Clear to disable SPTE interrupt generation
Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag
goes high. To enable SPIF interrupt again, SPTEIE should be cleared.
Interrupt Enable for MODF
Set and cleared by software:
- Set to enable MODF interrupt generation
- Clear to disable MODF interrupt generation
R5
5
R4
4
R3
3
R2
2
4182I–CAN–06/05
R1
1
R0
0