AT89C51CC03U-S3SIM ATMEL [ATMEL Corporation], AT89C51CC03U-S3SIM Datasheet - Page 42
AT89C51CC03U-S3SIM
Manufacturer Part Number
AT89C51CC03U-S3SIM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51CC03U-S3SIM.pdf
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External Code Memory Access
Memory Interface
External Bus Cycles
42
AT89C51CC03
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (PSEN#, and ALE).
Figure 21 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21
describes the external memory interface signals.
Figure 21. External Code Memory Interface Structure
Table 12. External Code Memory Interface Signals
This section describes the bus cycles the AT89C51CC03 executes to fetch code (see
Figure 22) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode see section “Clock “.
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
For bus cycling parameters refer to the ‘AC-DC parameters’ section.
Signal
PSEN#
Name
AD7:0
A15:8
ALE
Type
I/O
O
O
O
Description
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
Program Store Enable Output
This signal is active low during external code fetch or external code read
(MOVC instruction).
AT89C51CC0
PSEN#
ALE
P2
P0
AD7:0
A15:8
Latch
A7:0
A15:8
A7:0
D7:0
OE
EPROM
Flash
4182I–CAN–06/05
Alternate
Function
P2.7:0
P0.7:0
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