HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 224

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HD6417034B

Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 9 Direct Memory Access Controller (DMAC)
1. Transfer requests are generated simultaneously for channels 1 and 0.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 1 waits for
3. A channel 3 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 becomes the lowest priority.
5. At this point, channel 3 has a higher priority than channel 1, so the channel 3 transfer begins
6. When the channel 3 transfer ends, channel 3 becomes the lowest priority.
7. The channel 1 transfer begins.
8.
Rev. 7.00 Jan 31, 2006 page 198 of 658
REJ09B0272-0700
transfer).
waiting)
(channel 1 waits for transfer).
When the channel 1 transfer ends, channels 1 and 2 shift downward in priority so that channel
1 becomes the lowest priority.
(1) Channels 0 and 1
Transfer request
(3) Channel 3
Figure 9.4 Changes in Channel Priority in Round-Robin Mode
Waiting channel(s)
1
1, 3
1
None
(2) Channel 0
(4) Channel 0
(5) Channel 3
(6) Channel 3
(7) Channel 1
(8) Channel 1
DMAC operation
transfer starts
transfer ends
transfer starts
transfer ends
transfer starts
transfer ends
Priority order
Priority order
Priority order
changes
changes
changes
Channel priority
0
3
2
0
3
2
1
3
2
1
0
2
1
0
3
1

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