HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 311
HD6417034B
Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417034B.pdf
(687 pages)
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Reset-Synchronized PWM Mode: The BR value is transferred to GR upon a GRA3 compare
match.
Procedure for Selecting Buffer Mode (Figure 10.47):
1. Set TIOR to select the output compare or input capture function of GR.
2. Set bits BFA3, BFB3 and BFB4 in TFCR to select buffer mode for GR.
3. Set the STR bit in TSTR to 1 to start the TCNT count.
Buffer Mode Operation: Figure 10.48 shows an example of an operation in buffer mode with
GRA set as an output compare register and GRA and buffer register A (BRA) set for buffer
operation. TCNT operates as a periodic counter that is cleared by a GRB compare match. TIOCA
and TIOCB are set to toggle at compare matches A and B. Since buffer mode is selected, when
TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA. This
operation is repeated at every compare match A. The transfer timing is shown in figure 10.49.
Figure 10.47 Procedure for Selecting Buffer Mode
Select general register function
Select buffer mode
Start counting
Buffer mode
Buffer mode
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Rev. 7.00 Jan 31, 2006 page 285 of 658
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REJ09B0272-0700
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