HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 268
HD6417034B
Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417034B.pdf
(687 pages)
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Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.2.6
The ITU has five 16-bit timer counters (TCNT), one for each channel.
Each TCNT is a 16-bit read/write counter that counts by input from a clock source. The clock
source is selected by timer prescaler bits 2–0 (TPSC2–TPSC0) in the timer control register (TCR).
TCNT0 and TCNT 1 are strictly up-counters. Up/down-counting occurs for TCNT2 when phase
counting mode is selected, or for TCNT3 and TCNT 4 when complementary PWM mode is
selected. In other modes, they are up-counters.
TCNT can be cleared to H'0000 by compare match with the corresponding general register A or B
(GRA, GRB) or input capture to GRA or GRB (counter clear function).
When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) in the timer
status register (TSR) is set to 1. The OVF of the corresponding channel TSR is also set to 1 when
TCNT underflows (changes from H'0000 to H'FFFF).
TCNT is connected to the CPU by a 16-bit bus, so it can be written or read by either word access
or byte access. TCNT is initialized to H'0000 by a reset and in standby mode.
Table 10.4 Timer Counters (TCNT)
Channel
0
1
2
3
4
Rev. 7.00 Jan 31, 2006 page 242 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Timer Counters (TCNT)
Abbreviation
TCNT0
TCNT1
TCNT2
TCNT3
TCNT4
R/W
R/W
15
0
7
0
Function
Increment counter
Phase counting mode: Increment/decrement
All others: Increment
Complementary PWM mode: Increment/decrement
All others: Increment
R/W
R/W
14
0
6
0
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
R/W
R/W
8
0
0
0
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