HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 89
HD6417034B
Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417034B.pdf
(687 pages)
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4.6
In some cases, address errors and interrupts that directly follow a delayed branch instruction or
interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this
occurs, the exception is accepted when an instruction that can accept the exception is decoded.
Table 4.9
Case
Immediately after delayed branch instruction *
Immediately after interrupt-disabled instruction *
X: Not accepted
O: Accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE
4.6.1
Address errors and interrupts are not accepted when an instruction in a delay slot immediately
following a delayed branch instruction is decoded. The delayed branch instruction and the
instruction in the delay slot are therefore always executed one after the other. Exception handling
is never inserted between them.
4.6.2
Interrupts are not accepted when the instruction immediately following an interrupt-disabled
instruction is decoded. Address errors are accepted, however.
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
Cases in which Exceptions are Not Accepted
Immediately after Delayed Branch Instruction
Immediately after Interrupt-Disabling Instruction
Cases in which Exceptions are Not Accepted
1
2
Address Error
X
O
Rev. 7.00 Jan 31, 2006 page 63 of 658
Exception Source
Section 4 Exception Handling
Interrupt
X
X
REJ09B0272-0700
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