NAND02G-B2D NUMONYX [Numonyx B.V], NAND02G-B2D Datasheet - Page 17

• Manufacturer Part Number: NAND02G-B2D
• Description: 2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

NAND02G-B2D
4
4.1
4.2
4.3
4.4
Bus operations
There are six standard bus operations that control the memory, as described in this section.
See
Typically, glitches of less than 5 ns on Chip Enable, Write Enable, and Read Enable are
ignored by the memory and do not affect bus operations.
Command input
Command input bus operations give commands to the memory.
Commands are accepted when Chip Enable is Low, Command Latch Enable is High,
Address Latch Enable is Low, and Read Enable is High. They are latched on the rising edge
of the Write Enable signal.
Only I/O0 to I/O7 input commands.
See
Address input
Address input bus operations input the memory addresses. Five bus cycles are required to
input the addresses (refer to
insertion (x 16
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input addresses.
See
Data input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See
Data output
Data output bus operations read the data in the memory array, the Status register, the
electronic signature, and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
Table 4: Bus operations
Figure 24
Figure 25
Figure 26
and
devices)).
and
and
Table 27
Table 27
Table 27
for details of the timings requirements.
for details of the timings requirements.
and
for a summary of these operations.
Table 5: Address insertion (x 8 devices)
Table 28
for details of the timings requirements.
and
Table 6: Address
Bus operations
17/69