NAND02G-B2D NUMONYX [Numonyx B.V], NAND02G-B2D Datasheet - Page 29

• Manufacturer Part Number: NAND02G-B2D
• Description: 2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

NAND02G-B2D
Figure 13. Copy back program (without readout of data)
1. Copy back program is only permitted between odd address pages or even address pages.
Figure 14. Copy back program (with readout of data)
RB
RB
I/O
I/O
Read
Code
Read
Code
00h
00h
The NAND02G-B2D device features automatic EDC (error detection code) during a copy
back operation. Consequently, external ECC is no longer required. The errors detected
during copy back operations can be read by performing a read EDC Status register
operation (see
EDC operations.
The copy back program operation requires the following four steps:
1.
2.
3.
To see the data input cycle for modifying the source page and an example of the copy back
program operation, refer to
Figure 15: Page copy back program with random data input
modify a portion or a multiple distant portion of the source page.
The first step reads the source page. The operation copies all 2112 bytes from the
page into the data buffer. It requires:
–
–
–
When the device returns to the ready state (Ready/Busy High), optional data readout is
allowed by pulsing R; the next bus write cycle of the command is given with the 5 bus
cycles to input the target page address. The address A18 in x 8 devices (A17 in x 16
devices) must be the same for the source and target page
Then, the confirm command is issued to start the P/E/R controller.
Add Inputs
Add Inputs
Source
Source
1 bus write cycle to set up the command
5 bus write cycles to input the source page address
1 bus write cycle to issue the confirm command code
(Read Busy time)
(Read Busy time)
Section 6.13: Read EDC status
tBLBH1
tBLBH1
35h
35h
Busy
Busy
Figure 13: Copy back program (without readout of
Copy Back
Data Outputs
Code
85h
Add Inputs
Copy Back
Target
Code
85h
register). See also
Add Inputs
Target
(Program Busy time)
shows a data input cycle to
tBLBH2
(Program Busy time)
10h
Section 6.9
tBLBH2
Busy
10h
Read Status Register
Device operations
70h
Busy
data).
for details of
SR0
70h
Read Status
Register
ai09858c
ai09858b
SR0
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