NAND02G-B2D NUMONYX [Numonyx B.V], NAND02G-B2D Datasheet - Page 32

• Manufacturer Part Number: NAND02G-B2D
• Description: 2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

Device operations
6.7
Figure 17. Block erase
32/69
RB
I/O
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of the following three steps (refer to
1.
2.
3.
The operation is initiated on the rising edge of Write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the Write Status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Block erase
setup code
One bus cycle is required to set up the Block Erase command. Only addresses A18-
A28 are used; the other address inputs are ignored
Three bus cycles are then required to load the address of the block to be erased. Refer
to
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
60h
Table 7: Address definition (x 8 devices)
Block address
inputs
Confirm
code
D0h
for the block addresses of each device
(Erase Busy time)
tBLBH3
Busy
Figure 17: Block
Read Status Register
70h
NAND02G-B2D
SR0
erase):
ai07593