NAND02G-B2D NUMONYX [Numonyx B.V], NAND02G-B2D Datasheet - Page 44

• Manufacturer Part Number: NAND02G-B2D
• Description: 2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories
• Manufacturer: NUMONYX [Numonyx B.V]

Data protection
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Data protection
The devices feature a Write Protect, WP, pin, which protects the device against program and
erase operations. It is recommended to keep WP at V
Software algorithms
This section provides information on the software algorithms that Numonyx recommends
implementing to manage the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are programmed and erased by Fowler-Nordheim tunnelling using
high voltage. Exposing the device to high voltage for extended periods damages the oxide
layer.
To extend the number of program and erase cycles and increase the data retention, the:
To help integrate a NAND memory into an application, Numonyx provides a file system OS
native reference software, which supports the basic commands of file management.
Contact the nearest Numonyx sales office for more details.
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices that have all valid blocks. A bad block does not affect the
performance of valid blocks because it is isolated from the bit and common source lines by a
select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 1st and 6th bytes or the
1st word in the spare area of the 1st page, does not contain FFh, is a bad block.
The bad block information must be read before any erase is attempted as the bad block
Information may be erased. For the system to be able to recognize the bad blocks based on
the original information, the creation of a bad block table following the flowchart shown in
Figure 20: Bad block management flowchart
Number of program and erase cycles is limited (see
program erase endurance cycles
Implementation of a garbage collection, a wear-leveling algorithm and an error
correction code is recommended.
for the values)
is recommended.
IL
during power-up and power-down.
Table 21: Program erase times and
NAND02G-B2D