E28F016XS20 INTEL [Intel Corporation], E28F016XS20 Datasheet - Page 12

• Manufacturer Part Number: E28F016XS20
• Description: 16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
• Manufacturer: INTEL [Intel Corporation]

28F016XS FLASH MEMORY
2.1
12
A
A
A
A
DQ
DQ
CE
RP#
OE#
WE#
0
1
2
17
Symbol
–A
0
–A
0
8
#, CE
–DQ
–DQ
16
20
Lead Descriptions
7
15
1
#
OUTPUT
OUTPUT
INPUT/
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
BYTE-SELECT ADDRESS: Selects between high and low byte when device is
in x8 mode. This address is latched in x8 data programs and ignored in x16
mode (i.e., the A
BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block.
A 128-Kbyte block is subdivided into an even and odd bank. A
even bank and A
wide mode device configurations.
WORD-SELECT ADDRESSES: Select a word within one 128-Kbyte block.
Address A
columns. These addresses are latched during both data reads and programs.
BLOCK-SELECT ADDRESSES: Select 1 of 16 erase blocks. These
addresses are latched during data programs, erase and lock-block operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, identifier or status data in the appropriate read mode. Floated
when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS: Inputs data during x16 data program operations.
Outputs array or identifier data in the appropriate read mode; not used for
Status Register reads. Outputs floated when the chip is de-selected, the
outputs are disabled (OE# = V
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE
de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE
CE
All timing specifications are the same for both signals. Device Selection occurs
with the latter falling edge of CE
CE
RESET/POWER-DOWN: RP# low places the device in a deep power-down
state. All circuits that consume static power, even those circuits enabled in
standby mode, are turned off. When returning from deep power-down, a
recovery time of t
When RP# goes low, the current WSM operation is terminated, and the device
is reset. All Status Registers return to ready, clearing all status flags. Exit from
deep power-down places the device in read array mode.
OUTPUT ENABLE: Drives device data through the output buffers when low.
The outputs float to tri-state off when OE# is high. CE x # overrides OE#, and
OE# overrides WE#.
WRITE ENABLE: Controls access to the CUI, Data Register and Address
Latch. WE# is active low, and latches both address and data (command or
array) on its rising edge.
1
1
# must be low to select the device.
# disables the device.
1
and A
0
1
PHCH
7–16
input buffer is turned off when BYTE# is high).
= 1 selects the odd bank, in both byte-wide mode and word-
select 1 of 2048 rows, and A
is required to allow these circuits to power-up.
Name and Function
IH
) or BYTE# is driven active.
0
# or CE
1
#. The first rising edge of CE
0
# or CE
2–6
select 16 of 512
1
# high, the device is
1
= 0 selects the
0
# and
0
# or