DSPIC30F6010 MICROCHIP [Microchip Technology], DSPIC30F6010 Datasheet - Page 133

• Manufacturer Part Number: DSPIC30F6010
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

20.7
The analog input model of the 10-bit A/D converter is
shown in Figure 20-2. The total sampling time for the
A/D is a function of the internal amplifier settling time,
device V
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the voltage level on the analog input
pin. The source impedance (R
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D con-
verter, the maximum recommended source imped-
ance, R
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 20-2:
 2004 Microchip Technology Inc.
SS
) impedance combine to directly affect the time
S
DD
A/D Acquisition Requirements
, is 5 kΩ. After the analog input channel is
and the holding capacitor charge time.
Note: C
IC
), and the internal sampling switch
Legend: C
VA
PIN
Rs
A/D CONVERTER ANALOG INPUT MODEL
value depends on device package and is not tested. Effect of C
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
C
PIN
HOLD
S
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
), the interconnect
various junctions
) must be allowed
. The combined
V
DD
V
V
T
T
= 0.6V
= 0.6V
Preliminary
R
I leakage
± 500 nA
IC
≤ 250Ω
The user must allow at least 1 T
time, T
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the A/D con-
verter. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Electrical Specifications for T
requirements.
SAMP
Sampling
Switch
R
, between conversions to allow each sam-
SS
PIN
dsPIC30F6010
R
negligible if Rs ≤ 5 kΩ.
SS
V
SS
C
= DAC capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
AD
AD
DS70119D-page 131
period of sampling
and sample time