DSPIC30F6010 MICROCHIP [Microchip Technology], DSPIC30F6010 Datasheet - Page 84

• Manufacturer Part Number: DSPIC30F6010
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6010
14.7.2
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit
(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been
entered.
DS70119D-page 82
timer
TIMER OPERATION DURING CPU
IDLE MODE
will
operate
if
the
QEISIDL
Preliminary
bit
14.8
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
• Detection of qualified index pulse, or if CNTERR
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 Status register.
Enabling an interrupt is accomplished via the respec-
tive Enable bit, QEIIE. The QEIIE bit is located in the
IEC2 Control register.
rollover/underflow
bit is set
Quadrature Encoder Interface
Interrupts
 2004 Microchip Technology Inc.