DSPIC30F6010 MICROCHIP [Microchip Technology], DSPIC30F6010 Datasheet - Page 93

• Manufacturer Part Number: DSPIC30F6010
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 15-4:
15.8
An independent PWM Output mode is required for driv-
ing certain types of loads. A particular PWM output pair
is in the Independent Output mode when the corre-
sponding PMOD bit in the PWMCON1 register is set.
No dead time control is implemented between adjacent
PWM I/O pins when the module is operating in the
Independent mode and both I/O pins are allowed to be
active simultaneously.
In the Independent mode, each duty cycle generator is
connected to both of the PWM I/O pins in an output
pair. By using the associated duty cycle register and
the appropriate bits in the OVDCON register, the user
may select the following signal output options for each
PWM I/O pin operating in the Independent mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
15.9
The PWM module produces single pulse outputs when
the PTCON control bits PTMOD<1:0> = 10. Only edge
aligned outputs may be produced in the Single Pulse
mode. In Single Pulse mode, the PWM I/O pin(s) are
driven to the active state when the PTEN bit is set.
When a match with a duty cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PTPER register occurs, the PTMR reg-
ister is cleared, all active PWM I/O pins are driven to
the inactive state, the PTEN bit is cleared, and an
interrupt is generated.
 2004 Microchip Technology Inc.
Time selected by DTSxA bit (A or B)
PWMxH
Duty Cycle Generator
PWMxL
Independent PWM Output
Single Pulse PWM Operation
DEAD TIME TIMING DIAGRAM
Preliminary
15.10 PWM Output Override
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states,
independent of the duty cycle comparison units.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains eight
bits, POVDxH<4:1> and POVDxL<4:1>, that determine
which PWM I/O pins will be overridden. The lower half
of
POUTxH<4:1> and POUTxL<4:1>, that determine the
state of the PWM I/O pins when a particular output is
overridden via the POVD bits.
15.10.1
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the comple-
ment of the corresponding PWMxH pin in the pair.
Dead time insertion is still performed when PWM
channels are overridden manually.
15.10.2
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time base. Synchronous
output overrides occur at the following times:
• Edge Aligned mode, when PTMR is zero.
• Center Aligned modes, when PTMR is zero and
when the value of PTMR matches PTPER.
the
OVDCON
COMPLEMENTARY OUTPUT MODE
OVERRIDE SYNCHRONIZATION
Time selected by DTSxI bit (A or B)
dsPIC30F6010
register
contains
DS70119D-page 91
eight
bits,