DSPIC30F6010 MICROCHIP [Microchip Technology], DSPIC30F6010 Datasheet - Page 212

• Manufacturer Part Number: DSPIC30F6010
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6010
Program and EEPROM Characteristics ............................ 174
Program Counter................................................................. 12
Program Data Table Access ............................................... 22
Program Space Visibility
Programmable................................................................... 135
Programmable Digital Noise Filters..................................... 81
Programmer’s Model........................................................... 12
Programming Operations .................................................... 45
Protection Against Accidental Writes to OSCCON ........... 140
PWM Duty Cycle Comparison Units ................................... 89
PWM Fault Pins .................................................................. 92
PWM Operation During CPU Idle Mode.............................. 93
PWM Operation During CPU Sleep Mode .......................... 93
PWM Output and Polarity Control ....................................... 92
PWM Output Override......................................................... 91
PWM Period ........................................................................ 88
PWM Special Event Trigger ................................................ 93
PWM Time Base ................................................................. 87
PWM Update Lockout ......................................................... 93
Q
QEA/QEB Input Characteristics ........................................ 188
QEI Module
Quadrature Decoder Timing Requirements ...................... 188
Quadrature Encoder Interface (QEI) Module ...................... 79
Quadrature Encoder Interface Interrupts ............................ 82
Quadrature Encoder Interface Logic ................................... 80
DS70119D-page 210
Table Instructions
Window into Program Space Operation...................... 23
Diagram ...................................................................... 13
Algorithm for Program Flash ....................................... 45
Erasing a Row of Program Memory ............................ 45
Initiating the Programming Sequence ......................... 46
Loading Write Latches ................................................ 46
Duty Cycle Register Buffers ........................................ 89
Enable Bits.................................................................. 92
Fault States ................................................................. 92
Modes ......................................................................... 92
Priority ......................................................................... 92
Output Pin Control ...................................................... 92
Complementary Output Mode ..................................... 91
Synchronization .......................................................... 91
Postscaler ................................................................... 93
Continuous Up/Down Counting Modes ....................... 87
Double Update Mode .................................................. 88
Free Running Mode .................................................... 87
Postscaler ................................................................... 88
Prescaler ..................................................................... 88
Single Shot Mode........................................................ 87
External Clock Timing Requirements........................ 184
Index Pulse Timing Characteristics........................... 189
Index Pulse Timing Requirements ............................ 189
Operation During CPU Idle Mode ............................... 81
Operation During CPU Sleep Mode ............................ 81
Register Map............................................................... 83
Timer Operation During CPU Idle Mode ..................... 82
Timer Operation During CPU Sleep Mode.................. 81
TBLRDH.............................................................. 21
TBLRDL .............................................................. 21
TBLWTH ............................................................. 21
TBLWTL.............................................................. 21
Cycle-by-Cycle.................................................... 92
Latched ............................................................... 92
Preliminary
R
Reset ........................................................................ 135, 141
Reset Sequence ................................................................. 39
Reset Timing Characteristics............................................ 180
Reset Timing Requirements ............................................. 181
Resets
S
Simple Capture Event Mode
Simple OC/PWM Mode Timing Requirements ................. 186
Simple Output Compare Match Mode ................................ 76
Simple PWM Mode ............................................................. 76
Single Pulse PWM Operation ............................................. 91
Software Simulator (MPLAB SIM) .................................... 158
Software Simulator (MPLAB SIM30) ................................ 158
Software Stack Pointer, Frame Pointer .............................. 12
SPI Mode
SPI Module ......................................................................... 95
SPI Operation During CPU Idle Mode ................................ 97
SPI Operation During CPU Sleep Mode............................. 97
Status Register ................................................................... 12
Symbols Used in Opcode Descriptions ............................ 150
System Integration............................................................ 135
T
Temperature and Voltage Specifications
Timer1 Module.................................................................... 57
Reset Sources ............................................................ 39
BOR, Programmable ................................................ 143
POR .......................................................................... 141
POR with Long Crystal Start-up Time....................... 143
POR, Operating without FSCM and PWRT .............. 143
Capture Buffer Operation............................................ 72
Capture Prescaler....................................................... 71
Hall Sensor Mode ....................................................... 72
Input Capture in CPU Idle Mode................................. 72
Timer2 and Timer3 Selection Mode............................ 72
Input Pin Fault Protection ........................................... 76
Period ......................................................................... 77
CALL Stack Frame ..................................................... 27
Slave Select Synchronization ..................................... 97
SPI1 Register Map...................................................... 98
SPI2 Register Map...................................................... 98
Framed SPI Support ................................................... 97
Operating Function Description .................................. 95
SDOx Disable ............................................................. 95
Timing Characteristics
Timing Requirements
Word and Byte Communication .................................. 95
Overview................................................................... 135
Register Map ............................................................ 148
AC............................................................................. 175
DC ............................................................................ 163
16-bit Asynchronous Counter Mode ........................... 57
16-bit Synchronous Counter Mode ............................. 57
16-bit Timer Mode....................................................... 57
Master Mode (CKE = 0).................................... 190
Master Mode (CKE = 1).................................... 191
Slave Mode (CKE = 1).............................. 192, 193
Master Mode (CKE = 0).................................... 190
Master Mode (CKE = 1).................................... 191
Slave Mode (CKE = 0)...................................... 192
Slave Mode (CKE = 1)...................................... 194
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