DSPIC30F6010 MICROCHIP [Microchip Technology], DSPIC30F6010 Datasheet - Page 94

• Manufacturer Part Number: DSPIC30F6010
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6010
15.11 PWM Output and Polarity Control
There are three device configuration bits associated
with the PWM module that provide PWM output pin
control:
• HPOL configuration bit
• LPOL configuration bit
• PWMPIN configuration bit
These three bits in the FPORBOR configuration regis-
ter (see Section 21) work in conjunction with the four
PWM Enable bits (PWMEN<4:1>) located in the
PWMCON1 SFR. The configuration bits and PWM
Enable bits ensure that the PWM pins are in the correct
states after a device Reset occurs. The PWMPIN con-
figuration fuse allows the PWM module outputs to be
optionally enabled on a device Reset. If PWMPIN = 0,
the PWM outputs will be driven to their inactive states
at Reset. If PWMPIN = 1 (default), the PWM outputs
will be tri-stated. The HPOL bit specifies the polarity for
the PWMxH outputs, whereas the LPOL bit specifies
the polarity for the PWMxL outputs.
15.11.1
The PEN<4:1>H and PEN<4:1>L control bits in the
PWMCON1 SFR enable each high PWM output pin
and each low PWM output pin, respectively. If a partic-
ular PWM output pin not enabled, it is treated as a
general purpose I/O pin.
15.12 PWM FAULT Pins
There are two FAULT pins (FLTA and FLTB) associated
with the PWM module. When asserted, these pins can
optionally drive each of the PWM I/O pins to a defined
state.
15.12.1
The FLTACON and FLTBCON SFRs each have 4 con-
trol bits that determine whether a particular pair of
PWM I/O pins is to be controlled by the FAULT input
pin. To enable a specific PWM I/O pin pair for FAULT
overrides, the corresponding bit should be set in the
FLTACON or FLTBCON register.
If all enable bits are cleared in the FLTACON or
FLTBCON registers, then the corresponding FAULT
input pin has no effect on the PWM module and the pin
may be used as a general purpose interrupt or I/O pin.
DS70119D-page 92
Note:
OUTPUT PIN CONTROL
FAULT PIN ENABLE BITS
The FAULT pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the FLTACON/FLTBCON register are
cleared, then the FAULT pin(s) could be
used as general purpose interrupt pin(s).
Each FAULT pin has an interrupt vector,
Interrupt Flag bit and Interrupt Priority bits
associated with it.
Preliminary
15.12.2
The FLTACON and FLTBCON special function regis-
ters have 8 bits each that determine the state of each
PWM I/O pin when it is overridden by a FAULT input.
When these bits are cleared, the PWM I/O pin is driven
to the inactive state. If the bit is set, the PWM I/O pin
will be driven to the active state. The active and inactive
states are referenced to the polarity defined for each
PWM I/O pin (HPOL and LPOL polarity control bits).
A special case exists when a PWM module I/O pair is
in the Complementary mode and both pins are pro-
grammed to be active on a FAULT condition. The
PWMxH pin always has priority in the Complementary
mode, so that both I/O pins cannot be driven active
simultaneously.
15.12.3
If both FAULT input pins have been assigned to control
a particular PWM I/O pin, the FAULT state programmed
for the FAULT A input pin will take priority over the
FAULT B input pin.
15.12.4
Each of the FAULT input pins has two modes of
operation:
• Latched Mode: When the FAULT pin is driven
• Cycle-by-Cycle Mode: When the FAULT input
The Operating mode for each FAULT input pin is
selected using the FLTAM and FLTBM control bits in
the FLTACON and FLTBCON Special Function
Registers.
Each of the FAULT pins can be controlled manually in
software.
low, the PWM outputs will go to the states defined
in the FLTACON/FLTBCON register. The PWM
outputs will remain in this state until the FAULT
pin is driven high and the corresponding interrupt
flag has been cleared in software. When both of
these actions have occurred, the PWM outputs
will return to normal operation at the beginning of
the next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the FAULT condi-
tion ends, the PWM module will wait until the
FAULT pin is no longer asserted, to restore the
outputs.
pin is driven low, the PWM outputs remain in the
defined FAULT states for as long as the FAULT
pin is held low. After the FAULT pin is driven high,
the PWM outputs return to normal operation at the
beginning of the following PWM cycle or
half-cycle boundary.
FAULT STATES
FAULT PIN PRIORITY
FAULT INPUT MODES
 2004 Microchip Technology Inc.