LM3S1911-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S1911-IQC20-A0 Datasheet - Page 34

• Manufacturer Part Number: LM3S1911-IQC20-A0
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

ARM Cortex-M3 Processor Core
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
34
Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris
Cortex™-M3 Technical Reference Manual can be ignored.
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S1911 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■
■
■
Debug
Slave
Slave
APB
ATB
Port
Port
Facilitates low-latency exception and interrupt handling
Controls power management
Implements system control registers
Interface
Interface
APB
ATB
®
devices have implemented TPIU as shown in Figure 2-2 on page 34.
Asynchronous FIFO
Preliminary
®
devices. This means Chapters 15 and 16 of the ARM®
(serializer)
Trace Out
Serial Wire
Trace Port
(SWO)
October 09, 2007