LM3S1911-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S1911-IQC20-A0 Datasheet - Page 8

• Manufacturer Part Number: LM3S1911-IQC20-A0
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 7-1.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 301
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 302
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 302
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
Figure 14-8.
Figure 14-9.
Figure 14-10. Master Burst RECEIVE .................................................................................................. 338
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 339
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 340
8
Stellaris
CPU Block Diagram ......................................................................................................... 33
TPIU Block Diagram ........................................................................................................ 34
JTAG Module Block Diagram ............................................................................................ 43
Test Access Port State Machine ....................................................................................... 46
IDCODE Register Format ................................................................................................. 51
BYPASS Register Format ................................................................................................ 52
Boundary Scan Register Format ....................................................................................... 52
External Circuitry to Extend Reset .................................................................................... 54
Hibernation Module Block Diagram ................................................................................. 111
Flash Block Diagram ...................................................................................................... 129
GPIODATA Write Example ............................................................................................. 154
GPIODATA Read Example ............................................................................................. 154
GPTM Module Block Diagram ........................................................................................ 194
16-Bit Input Edge Count Mode Example .......................................................................... 198
16-Bit Input Edge Time Mode Example ........................................................................... 199
16-Bit PWM Mode Example ............................................................................................ 200
WDT Module Block Diagram .......................................................................................... 229
UART Module Block Diagram ......................................................................................... 253
UART Character Frame ................................................................................................. 254
IrDA Data Modulation ..................................................................................................... 256
SSI Module Block Diagram ............................................................................................. 293
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 295
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 296
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 297
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 297
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 298
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 299
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 299
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 300
I
I
START and STOP Conditions ......................................................................................... 331
Complete Data Transfer with a 7-Bit Address ................................................................... 332
R/S Bit in First Byte ........................................................................................................ 332
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 335
Master Single RECEIVE ................................................................................................. 336
Master Burst SEND ....................................................................................................... 337
2
2
C Block Diagram ......................................................................................................... 330
C Bus Configuration .................................................................................................... 331
®
1000 Series High-Level Block Diagram ............................................................... 25
Preliminary
2
C Bus ............................................................... 332
October 09, 2007