LM3S1911-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S1911-IQC20-A0 Datasheet - Page 73

• Manufacturer Part Number: LM3S1911-IQC20-A0
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:16
15:14
13:5
4:0
RO
RO
31
15
0
-
OD
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 69).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
RO
RO
30
14
0
-
reserved
Name
OD
RO
RO
R
29
13
F
0
-
RO
RO
28
12
0
-
RO
RO
Type
27
11
0
RO
RO
RO
RO
-
RO
RO
26
10
0
-
Reset
0x0
-
-
-
RO
RO
25
0
9
F
-
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL OD Value
This field specifies the value supplied to the PLL’s OD input.
PLL F Value
This field specifies the value supplied to the PLL’s F input.
PLL R Value
This field specifies the value supplied to the PLL’s R input.
RO
RO
Value
0x0
0x1
0x2
0x3
24
0
8
-
reserved
Description
Divide by 1
Divide by 2
Divide by 4
Reserved
RO
RO
23
0
7
-
RO
RO
22
0
6
-
RO
RO
21
0
5
-
RO
RO
20
0
4
-
LM3S1911 Microcontroller
RO
RO
19
0
3
-
RO
RO
18
R
0
2
-
RO
RO
17
0
1
-
RO
RO
16
0
0
-
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