HD64336901G Renesas Technology, HD64336901G Datasheet - Page 177

• Manufacturer Part Number: HD64336901G
• Description: (HD64xxx Series) 16-BIT MICROCONTROLLER
• Manufacturer: Renesas Technology

11.6
The following types of contention or operation can occur in timer V operation.
1.
2.
3.
4.
Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
11.12 shows the timing.
If compare matches A and B occur simultaneously, any conflict between the output selections
for compare match A and compare match B is resolved by the following priority: toggle
output
Depending on the timing, TCNTV may be incremented by a switch between different internal
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock ( ). Therefore, as shown
in figure 11.13 the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a
switch between internal and external clocks.
Usage Notes
output 1
Figure 11.11 Contention between TCNTV Write and Clear
Counter clear signal
Internal write signal
output 0.
Address
TCNTV
TCNTV write cycle by CPU
T
1
TCNTV address
N
T
2
Rev. 1.00, 11/03, page 149 of 376
T
3
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