HD64336901G Renesas Technology, HD64336901G Datasheet - Page 202

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HD64336901G

Manufacturer Part Number
HD64336901G
Description
(HD64xxx Series) 16-BIT MICROCONTROLLER
Manufacturer
Renesas Technology
Datasheet
12.5.3
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock ( ) cycles; shorter pulses will
not be detected correctly.
12.5.4
Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N + 1.
Rev. 1.00, 11/03, page 174 of 376
Input Capture Timing
Timing of Counter Clearing by Compare Match
Input capture
input
Input capture
signal
TCNT
GRA to GRD
Compare
match signal
TCNT
GRA
Figure 12.18 Timing of Counter Clearing by Compare Match
Figure 12.17 Input Capture Input Signal Timing
N–1
N
N
N
H'0000
N+1
N
N+2

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