HD64336901G Renesas Technology, HD64336901G Datasheet - Page 272

• Manufacturer Part Number: HD64336901G
• Description: (HD64xxx Series) 16-BIT MICROCONTROLLER
• Manufacturer: Renesas Technology

15.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
Rev. 1.00, 11/03, page 244 of 376
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
ICDRR
ICDRT
ICDRS
TDRE
TEND
SCL
SDA
SDA
SCL
User
TRS
Slave Receive Operation
Figure 15.10 Slave Transmit Mode Operation Timing (2)
A
9
Bit 7
1
Bit 6
2
Bit 5
3
Data n
Bit 4
[3] Clear TEND
4
Bit 3
5
Bit 2
6
[4] Read ICDRR (dummy read)
Bit 1
Slave transmit mode
after clearing TRS
7
Bit 0
8
9
[5] Clear TDRE
Slave receive
mode