T89C51CC02 Atmel, T89C51CC02 Datasheet - Page 122

• Manufacturer Part Number: T89C51CC02
• Description: 8-Bit MCU
• Manufacturer: Atmel

T89C51CC02
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts
at the same time.
Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a
bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each
combination.
A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A
high-priority interrupt cannot be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority
level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence, see Table 24.
122
CAN (Txok, Rxok, Err or OvrBuf)
CAN Timer Overflow (OVRTIM)
external interrupt (INT0)
external interrupt (INT1)
PCA (CF or CCFn)
Interrupt Name
UART (RI or TI)
Timer0 (TF0)
Timer1 (TF1)
Timer2 (TF2)
ADC (ADCI)
IPH.x
0
0
1
1
Table 24. Interrupt priority Within level
Table 23. Priority Level Bit Values
Interrupt Address Vector
Preliminary
IPL.x
000Bh
001Bh
002Bh
003Bh
004Bh
0003h
0013h
0033h
0023h
0043h
0
1
0
1
Interrupt Level Priority
Priority Number
3 (Highest)
0 (Lowest)
Rev.A - May 17, 2001
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