T89C51CC02 Atmel, T89C51CC02 Datasheet - Page 88

• Manufacturer Part Number: T89C51CC02
• Description: 8-Bit MCU
• Manufacturer: Atmel

T89C51CC02
CANBT2 (S:B5h)
CAN Bit Timing Registers 2
Note:
The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0.
See Figure 60.
No default value after reset.
88
Bit Number Bit Mnemonic
6-5
3-1
7
-
7
4
0
SJW 1
SJW1:0
PRS2:0
6
-
-
-
Reserved
Re-synchronization jump width
Reserved
Programming time segment
Reserved
SJW 0
The value read from this bit is indeterminate. Do not set this bit.
To compensate for phase shifts between clock oscillators of different bus controllers, the controller
must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period may be
shortened or lengthened by a re-synchronization.
The value read from this bit is indeterminate. Do not set this bit.
This part of the bit time is used to compensate for the physical delay times within the network. It is
twice the sum of the signal propagation time on the bus line, the input comparator delay and the
output driver delay.
The value read from this bit is indeterminate. Do not set this bit.
5
Figure 75. CANBT2 Register
Preliminary
4
-
Tsjw
Tprs
PRS 2
=
=
3
Tscl
Description
Tscl
SJW 1 0
PRS 2
PRS 1
2
+
0
1
+
1
PRS 0
Rev.A - May 17, 2001
1
0
-