T89C51CC02 Atmel, T89C51CC02 Datasheet - Page 68

• Manufacturer Part Number: T89C51CC02
• Description: 8-Bit MCU
• Manufacturer: Atmel

T89C51CC02
15. Atmel CAN Controller
15.1. Introduction
The Atmel CAN Controller provides all the features required to implement the serial communication protocol CAN
as defined by the BOSCH GmbH. The CAN specifications as referred to in ISO/11898 (2.0A & 2.0B) for high
speed and ISO/11519-2 for low speed are applied. The CAN Controller is able to handle all types of frames (Data,
Remote, Error and Overload) and achieves a bitrate of 1 Mbit/s at 8MHz
NOTE:
1. At BRP = 1 sampling point will be fixed.
15.2. CAN Controller Description
The CAN Controller accesses are made through SFR.
Several operations are possible by SFR:
arithmetic and logic operations, transfers and program control (SFR is accessible by direct addressing).
4 independent message objects are implemented, a pagination system manages their accesses.
Any message object can be programmed in a reception buffer block (even non-consecutive buffers). For the
reception of defined messages one or several receiver message objects can be masked without participating in the
buffer feature. An IT is generated when the buffer is full. The frames following the buffer-full interrupt will not
be taken into account until at least one of the buffer message objects is re-enabled in reception. Higher priority
of a message object for reception or transmission is given to the lower message object number.
The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent message in the CANSTMP
register. This timer starts counting as soon as the CAN controller is enabled by the ENA bit in the CANGCON register.
The Time Trigger Communication (TTC) protocol is supported by the T89C51CC02.
68
TxDC
RxDC
Register
Page
Timing
Logic
Bit
Figure 56. CAN Controller block diagram
Interface
Preliminary
Bus
C-Core Interface
DPR(Mailbox + Registers)
Counter
Rec/Tec
Error
Control
Core
1
Receive
Crystal frequency in X2 mode.
Stuffing /Destuffing
Redundancy Check
Cyclic
Bit
Transmit
Encoder
Priority
Rev.A - May 17, 2001