T89C51CC02 Atmel, T89C51CC02 Datasheet - Page 89

• Manufacturer Part Number: T89C51CC02
• Description: 8-Bit MCU
• Manufacturer: Atmel

CANBT3 (S:B6h)
CAN Bit Timing Registers 3
Note:
The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0.
See Figure 60.
No default value after reset.
CANPAGE (S:B1h)
CAN message object Page Register
Reset Value: 0000 0000b
Rev.A - May 17, 2001
Bit Number Bit Mnemonic
Bit Number Bit Mnemonic
6-4
3-1
7-6
5-4
2-0
7
7
0
7
3
-
-
CHNB1:0
PHS2 2:0
PHS1 2:0
PHS2 2
INDX2:0
AINC
SMP
6
6
-
-
-
Reserved
Phase segment 2
Phase segment 1
Sample type
Reserved
Selection of message object number
Auto increment of the index (active low)
Index
CHNB 1
PHS2 1
The value read from this bit is indeterminate. Do not set this bit.
This phase is used to compensate for phase edge errors. This segment can be shortened by the re-
synchronization jump width.
This phase is used to compensate for phase edge errors. This segment can be lengthened by the re-
synchronization jump width.
0 - once, at the sample point.
1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a
1/2 period of the Tscl. The result corresponds to the majority decision of the three values.
The value read from these bit are indeterminate. Do not set these bits.
The available numbers are: 0 to 3 (see Figure 57).
0 - auto-increment of the index (default value).
1 - non-auto-increment of the index.
Byte location of the data field for the defined message object (see Figure 57).
5
5
Figure 77. CANPAGE Register
Figure 76. CANBT3 Register
Preliminary
CHNB 0
PHS2 0
4
4
Tphs2
Tphs1
PHS1 2
AINC
=
=
3
3
Tscl
Tscl
Description
Description
PHS2 2
PHS1 2
PHS1 1
INDX2
2
2
T89C51CC02
0
0
+
+
1
1
PHS1 0
INDX1
1
1
INDX0
SMP
0
0
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