AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 140

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

CSR17: Initialization Block Address Upper
Bit
31-16
15-0
CSR18: Current Receive Buffer Address Lower
Bit
31-16
15-0
CSR19: Current Receive Buffer Address Upper
Bit
31-16
15-0
CSR20: Current Transmit Buffer Address Lower
Bit
31-16
15-0
140
Name
RES
IADRH
Name
RES
CRBAL
Name
RES
CRBAU
Name
RES
CXBAL
zeros and read as undefined.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
zeros and read as undefined.
current receive buffer address at
which
Am79C975 controller will store
incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
current receive buffer address at
which
Am79C975 controller will store
incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
current transmit buffer address
from
Description
Reserved locations. Written as
This register is an alias of CSR2.
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
which
the
the
the
Am79C973/
Am79C973/
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
CSR21: Current Transmit Buffer Address Upper
Bit
31-16 RES
15-0
CSR22: Next Receive Buffer Address Lower
Bit
31-16
15-0
CSR23: Next Receive Buffer Address Upper
Bit
31-16 RES
15-0
Name
CXBAU
Name
Name
NRBAU
NRBAL
RES
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
next receive buffer address to
which
Am79C975 controller will store
incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Am79C975 controller is transmit-
ting.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
current transmit buffer address
from
Am79C975 controller is transmit-
ting.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next receive buffer address to
which
Am79C975 controller will store
incoming frame data.
which
the
the
the
Am79C973/
Am79C973/
Am79C973/