AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 155

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

10 PME_EN_OVR PME_EN Overwrite. When this
9
8
7
6
LCDET
LCMODE
EMPPLBA
PMAT
bit is set and the MPMAT or
LCDET bit is set, the PME pin will
always be asserted regardless of
the state of PME_EN bit.
Read/Write accessible only when
either the STOP bit or the SPND
bit is set. Cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Link Change Detected. This bit is
set when the MII auto-polling log-
ic detects a change in link status
and the LCMODE bit is set.
LCDET is cleared when power is
initially applied (POR).
Read/Write accessible always.
Link Change Wake-up Mode.
When this bit is set to 1, the
LCDET bit gets set when the MII
auto polling logic detects a Link
Change.
Read/Write accessible only when
either the STOP bit or the SPND
bit is set. Cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Pattern Matched. This bit is set
when the PMMODE bit is set and
an OnNow pattern match occurs.
PMAT is cleared when power is
initially applied (POR).
Read accessible always.
Magic Packet Physical Logical
Broadcast Accept. If both EMP-
PLBA and MPPLBA (CSR5, bit 5)
are at their default value of 0, the
Am79C973/Am79C975 controller
will only detect a Magic Packet
frame if the destination address
of the packet matches the con-
tent of the physical address regis-
ter (PADR). If either EMPPLBA or
MPPLBA is set to 1, the destina-
tion address of the Magic Packet
frame can be unicast, multicast,
or broadcast. Note that the set-
ting of EMPPLBA and MPPLBA
P R E L I M I N A R Y
Am79C973/Am79C975
5
4
3 RWU_DRIVER RWU Driver Type. If this bit is set
2
RWU_GATE
MPMAT
MPPEN
Magic Packet Match. This bit is
Read/Write accessible always.
EMPPLBA
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
set when PCnet-FAST+ detects a
Magic Packet while it is in the
Magic Packet mode.
MPMAT is cleared when power is
initially applied (POR).
Read/Write accessible always.
Magic Packet Pin Enable. When
this bit is set, the device enters
the Magic Packet mode when the
PG input goes LOW or MPEN bit
(CSR5, bit 2) gets set to 1. This
bit is OR’ed with MPEN bit
(CSR5, bit 2).
Read/Write is accessible only
when either the STOP bit or the
SPND bit is set. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
to 1, RWU is a totem pole driver;
otherwise RWU is an open drain
output.
Read/Write is accessible only
when either the STOP bit or the
SPND bit is set. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
RWU Gate Control. If this bit is
set, RWU is forced to the high Im-
pedance State when PG is LOW,
regardless of the state of the MP-
MAT and LCDET bits.
Read/Write accessible only when
either the STOP bit or the SPND
only affects the address detection
of the Magic Packet frame. The
Magic Packet frame’s data se-
quence must be made up of 16
consecutive physical addresses
(PADR[47:0]) regardless of what
kind of destination address it has.
is
set
to
0
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by