AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 186

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

10-8
7
6
186
110-111
APDW
000
001
010
011
100
101
APDW
DANAS
XPHYRST
Continuous (26 s @ 2.5 MHz)
Every 128 MDC cycles (103 s @ 2.5 MHz)
Every 256 MDC cycles (206 s @ 2.5 MHz)
Every 512 MDC cycles (410 s @ 2.5 MHz)
Every 1024 MDC cycles (819 s @ 2.5 MHz)
Every 2048 MDC cycles (1640 s @ 2.5 MHz)
Reserved
Table 38. APDW Values
Auto-Poll Dwell Time. APDW de-
termines the dwell time between
PHY
accesses
turned on. See Table 38.
Read/Write accessible always.
APDW is set to 100h after
H_RESET and is unaffected by
S_RESET and the STOP bit.
Disable Auto-Negotiation Auto
Setup. When DANAS is set, the
Am79C973/Am79C975 controller
after a H_RESET or S_RESET
will remain dormant and not auto-
matically startup the Auto-Negoti-
ation section or the enhanced
automatic port selection section.
Instead,
Am79C975 controller will wait for
the software driver to setup the
Auto-Negotiation portions of the
device. The PHY Address and
Data programming in BCR33 and
BCR34
Am79C973/Am79C975 controller
will not generate any manage-
ment frames unless Auto-Poll is
enabled.
PHY Reset. When XPHYRST is
set, the Am79C973/Am79C975
controller after an H_RESET or
S_RESET will issue manage-
ment frames that will reset the
Read/Write accessible always.
APEP
H_RESET and is unaffected by
S_RESET and the STOP bit.
Read/write accessible always.
DANAS is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
Auto-Poll
is
Management
is
Dwell Time
when
set
the
still
to
Auto-Poll
valid.
Am79C973/
P R E L I M I N A R Y
0
Am79C973/Am79C975
Frame
during
The
is
5
4
3
2
1
XPHYANE
XPHYFD
XPHYSP
RES
MIIILP
Media Independent Interface In-
PHY. This bit is needed when
there is no way to guarantee the
state of the external PHY. This bit
must be reprogrammed after ev-
ery H_RESET.
Read/Write accessible always.
XPHYRST
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYRST is only valid when the
internal Network Port Manager is
scanning for a network port.
PHY Auto-Negotiation Enable.
This bit will force the PHY into en-
abling Auto-Negotiation. When
set
Am79C975 controller will send a
management
Auto-Negotiation.
Read/Write accessible always.
XPHYANE
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYANE is only valid when the
internal Network Port Manager is
scanning for a network port.
PHY Full Duplex. When set, this
bit will force the PHY into full du-
plex when Auto-Negotiation is not
enabled.
Read/Write accessible always.
XPHYFD
H_RESET, and is unaffected by
S_RESET and the STOP bit.
PHY Speed. When set, this bit
will force the PHY into 100 Mbps
mode when Auto-Negotiation is
not enabled.
Read/Write accessible always.
XPHYSP
H_RESET, and is unaffected by
S_RESET and the STOP bit.
Reserved location. Written as ze-
ros and read as undefined.
ternal Loopback. When set, this
bit will cause the internal portion
of the MII data port to loopback
on itself. The interface is mapped
in
the
to
following
0
is
is
is
is
the
frame
set
set
set
set
Am79C973/
way.
to
to
to
to
disabling
0
0
0
0
The
by
by
by
by