AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 141

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

CSR24: Base Address of Receive Ring Lower
Bit
31-16
15-0
CSR25: Base Address of Receive Ring Upper
Bit
31-16
15-0
CSR26: Next Receive Descriptor Address Lower
Bit
31-16
15-0
CSR27: Next Receive Descriptor Address Upper
Bit
Name
RES
BADRL
Name
RES
BADRU
Name
RES
NRDAL
Name
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Receive
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Receive
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next receive descriptor address
pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
P R E L I M I N A R Y
Am79C973/Am79C975
31-16 RES
15-0
CSR28: Current Receive Descriptor Address Lower
Bit
31-16 RES
15-0
CSR29: Current Receive Descriptor Address Upper
Bit
31-16 RES
15-0
CSR30: Base Address of Transmit Ring Lower
Bit
31-16 RES
15-0
NRDAU
Name
CRDAL
Name
CRDAU
Name
BADXL
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next receive descriptor address
pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
current receive descriptor ad-
dress pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
current receive descriptor ad-
dress pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
base address of the Transmit
Ring.
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