AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 200

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

ANR16: INTERRUPT Status and Enable Register (Register 16)
The Interrupt bits indicate when there is a change in the
Link Status, Duplex Mode, Auto-Negotiation status, or
Speed status. Register 16 contains the interrupt status
and interrupt enable bits. The status is always updated
Note:
1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.
ANR17: PHY Control/Status Register (Register 17)
This register is used to control the configuration of the
10/100 PHY unit of the Am79C973/Am79C975 device.
See Table 50.
When configuring the device to enable/disable the
scrambler/descrambler (SDISSCR), and/or to enable/
200
Bit(s)
15:14
7:5
13
12
11
10
9
8
4
3
2
1
0
Duplex Mode Change
Duplex Mode Change
Interrupt Test Enable
Link Status Change
Link Status Change
Auto-Neg Change
Auto-Neg Change
Interrupt Enable
Interrupt Enable
Interrupt Enable
Interrupt Enable
Interrupt Enable
Speed Change
Speed Change
Reserved
Reserved
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
(Note 1)
Global
Global
Name
Table 49. ANR16: INTERRUPT Status and Enable Register (Register 16)
1 = When this bit is set, setting bits 12:9 of this register
0 = Bits 4:1 are only set if the interrupt condition (if any
1 = Link Status Change
0 = This interrupt is masked.
1 = Duplex Mode Change
0 = This interrupt is masked.
1 = Auto-Neg Change
0 = This interrupt is masked.
1 = Speed Change
0 = This interrupt is masked.
1= Global Interrupt
0 = This interrupt is masked.
1 = Link Status has changed on a port.
0 = No change in Link Status
1 = Duplex Mode has changed on a port
0 = No change in Duplex mode
1 = Auto-Neg status has changed on a port
0 = No change in Auto-Neg status
1 = Speed status has changed on a port
0 = No change
1 = Indicates a change in status of any of the above
interrupts
0 = Indicates no change in Interrupt Status
will cause an INTR condition and will set bits 4:1
accordingly. The effect is to test the register bits with
a forced interrupt condition.
bits in 12:9 are set) occurs.
P R E L I M I N A R Y
Am79C973/Am79C975
Description
whether or not the interrupt enable bits are set. When
an interrupt occurs, the system will need to read the in-
terrupt register to clear the status bits and determine
the course of action needed. See Table 49.
disable the alignment (SDISALIGN), a software reset
after a write operation to the appropriate bits in this reg-
ister is mandatory for proper configuration. If a register
bit is only appropriate to use at one speed, then the
speed will be indicated in parenthesis in the Name col-
umn, for example, (10M).
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
RO,
RO,
RO,
RO,
RO,
RO
RO
LH
LH
LH
LH
LH
H/W or Soft
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0