AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 33

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

mode of operation. This pin is implemented for designs
that do not support the PME function.
Three bits that are loaded from the EEPROM into
CSR116 can program the characteristics of this pin:
1. RWU_POL determines the polarity of the RWU sig-
2. If RWU_GATE bit is set, RWU is forced to the high
3. RWU_DRIVER determines whether the output is
The internal power-on-reset signal forces this output
into the high impedance state until after the polarity and
drive type have been determined.
WUMI
Wake-Up Mode Indicator
This output, which is capable of driving an LED, is as-
serted when the device is in Magic Packet mode. It can
be used to drive external logic that switches the device
power source from the main power supply to an auxil-
iary power supply.
EEPROM Interface
EECS
EEPROM Chip Select
This pin is designed to directly interface to a serial EE-
PROM that uses the 93C46 EEPROM interface proto-
col. EECS is connected to the EEPROM’s chip select
pin. It is controlled by either the Am79C973/Am79C975
controller during command portions of a read of the en-
tire EEPROM, or indirectly by the host system by writ-
ing to BCR19, bit 2.
EEDI
EEPROM Data In
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface pro-
tocol. EEDI is connected to the EEPROM’s data input
pin. It is controlled by either the Am79C973/Am79C975
controller during command portions of a read of the en-
tire
by writing to BCR19, bit 0.
Note: The EEDI pin is multiplexed with the LED0 pin.
EEDO
EEPROM Data Out
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface pro-
tocol. EEDO is connected to the EEPROM’s data out-
put pin. It is controlled by either the Am79C973/
A m 7 9 C 9 7 5 A m 7 9 C9 7 3 / A m 7 9 C 9 7 5 A m 7 9 C 9 7 3 /
Am79C975 controller during command portions of a
nal.
impedance state when PG input is LOW.
open drain or totem pole.
EEPROM, or indirectly by the host system
P R E L I M I N A R Y
Am79C973/Am79C975
Output
Output
Output
Input
read of the entire EEPROM, or indirectly by the host
system by reading from BCR19, bit 0.
Note: The EEDO pin is multiplexed with the LED3 and
MIIRXFRTGD pins.
EESK
EEPROM Serial Clock
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface pro-
tocol. EESK is connected to the EEPROM’s clock pin.
It is controlled by either the Am79C973/Am79C975
controller directly during a read of the entire EEPROM,
or indirectly by the host system by writing to BCR19, bit
1.
Note: The EESK pin is multiplexed with the LED1 and
SFBD pins.
The EESK pin is also used during EEPROM Auto-
Detection to determine whether or not an EEPROM is
present at the Am79C973/Am79C975 controller inter-
face. At the rising edge of the last CLK edge while RST
is asserted, EESK is sampled to determine the value of
the EEDET bit in BCR19. A sampled HIGH value
means that an EEPROM is present, and EEDET will be
set to 1. A sampled LOW value means that an EE-
PROM is not present, and EEDET will be set to 0. See
the EEPROM Auto-Detection section for more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead to re-
solve the EEDET setting.
WARNING: The input signal level of EESK must be
valid for correct EEPROM detection before the
deassertion of RST.
Expansion Bus Interface
EBUA_EBA[7:0]
Expansion Bus Upper Address/
Expansion Bus Address [7:0]
The EBUA_EBA[7:0] pins provide the least and most
significant bytes of address on the Expansion Bus. The
most significant address byte (address bits [19:16] dur-
ing boot device accesses) is valid on these pins at the
beginning of a boot device access, at the rising edge of
AS_EBOE. This upper address byte must be stored ex-
ternally in a D flip-flop. During subsequent cycles of a
boot device access, address bits [7:0] are present on
these pins.
All EBUA_EBA[7:0] outputs are forced to a constant
level to conserve power while no access on the Expan-
sion Bus is being performed.
Note: EBUA_EBA[7:5] pins are multiplexed with the
TX_ER, PHY_RST, and MDC pins.
Output
Output
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