AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 296

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

CONNECTION DIAGRAM (PQL176)
CONNECTION DIAGRAM (PQL176)
CONNECTION DIAGRAM (PQR160) . . .18
CONNECTION DIAGRAM (PQR160)
Control and Status Registers . . .123, 214, 259
Control Register (Register 0) . . . . . . . . . . .274
CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
CSR0
CSR1
CSR10
CSR100
CSR11
CSR112
CSR114
CSR116
CSR12
CSR122
CSR124
CSR125
CSR13
CSR14
CSR15
CSR16
CSR17
296
Am79C973 . . . . . . . . . . . . . . . . . . . . . . . .19
Am79C975 . . . . . . . . . . . . . . . . . . . . . . . .21
Am79C975 . . . . . . . . . . . . . . . . . . . . . . . .20
Am79C972 Controller Status and
Initialization Block Address 0 . . . . . . .126
Logical Address Filter 2 . . . . . . . . . . .137
Bus Timeout . . . . . . . . . . . . . . . . . . . . .153
Logical Address Filter 3 . . . . . . . . . . .137
Missed Frame Count . . . . . . . . . . . . . .154
Receive Collision Count . . . . . . . . . . .154
OnNow Power Mode Register . . . . . . .154
Physical Address Register 0 . . . . . . . .137
Advanced Feature Control . . . . . . . . . .156
Test Register 1 . . . . . . . . . . . . . . . . . . .156
MAC Enhanced Configuration
Physical Address Register 1 . . . . . . . .137
Physical Address Register 2 . . . . . . . .137
Mode . . . . . . . . . . . . . . . . . . . . . . . . . .138
Initialization Block Address
Initialization Block Address
Control Register . . . . . . . . . . . . . . .123
Control . . . . . . . . . . . . . . . . . . . . . .156
Lower . . . . . . . . . . . . . . . . . . . . . . .139
P R E L I M I N A R Y
Am79C973/Am79C975
CSR18
CSR19
CSR2
CSR20
CSR21
CSR22
CSR23
CSR24
CSR25
CSR26
CSR27
CSR28
CSR29
CSR3
CSR30
CSR31
Current Receive Buffer Address
Lower . . . . . . . . . . . . . . . . . . . . . . . . . .140
Current Receive Buffer Address
Initialization Block Address 1 . . . . . . .126
Current Transmit Buffer Address
Current Transmit Buffer Address
Next Receive Buffer Address
Next Receive Buffer Address
Base Address of Receive Ring
Base Address of Receive Ring
Next Receive Descriptor Address
Next Receive Descriptor Address
Current Receive Descriptor Address
Current Receive Descriptor Address
Interrupt Masks and Deferral
Base Address of Transmit Ring
Base Address of Transmit Ring
Upper . . . . . . . . . . . . . . . . . . . . . . .140
Upper . . . . . . . . . . . . . . . . . . . . . . .140
Lower . . . . . . . . . . . . . . . . . . . . . . .140
Upper . . . . . . . . . . . . . . . . . . . . . . .140
Lower . . . . . . . . . . . . . . . . . . . . . . .140
Upper . . . . . . . . . . . . . . . . . . . . . . .140
Lower . . . . . . . . . . . . . . . . . . . . . . .141
Upper . . . . . . . . . . . . . . . . . . . . . . .141
Lower . . . . . . . . . . . . . . . . . . . . . . .141
Upper . . . . . . . . . . . . . . . . . . . . . . .141
Lower . . . . . . . . . . . . . . . . . . . . . . .141
Upper . . . . . . . . . . . . . . . . . . . . . . .141
Control . . . . . . . . . . . . . . . . . . . . . .126
Lower . . . . . . . . . . . . . . . . . . . . . . .141