AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 205

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

If the Logical Address Filter is loaded with all zeros and
promiscuous mode is disabled, all incoming logical ad-
dresses except broadcast will be rejected. If the
DRCVBC bit (CSR15, bit 14) is set as well, the broad-
cast packets will be rejected. See Figure 51.
PADR
This 48-bit value represents the unique node address
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and
used for internal address comparison. PADR[0] is com-
pared with the first bit in the destination address of the
incoming frame. It must be 0 since only the destination
address of a unicast frames is compared to PADR. The
six hex-digit nomenclature used by the ISO 8802-3
( I E E E / A N S I 8 0 2 . 3 ) m a p s t o t h e A m 7 9 C 9 7 3 /
Am79C975 PADR register as follows: the first byte is
Receive Descriptors
When SWSTYLE (BCR20, bits 7-0) is set to 0, then the
software structures are defined to be 16 bits wide, and
receive descriptors look like Table 58 (CRDA = Current
Receive Descriptor Address).
When SWSTYLE (BCR 20, bits 7-0) is set to 2, then the
software structures are defined to be 32 bits wide, and
CRDA+00h
CRDA+02h
CRDA+04h
CRDA+06h
Address
47
Match = 1 Packet Accepted
Match = 0 Packet Rejected
OWN
Received Message
Destination Address
15
1
0
ERR
14
1
0
Table 58. Receive Descriptor (SWSTYLE = 0)
1
1
0
FRAM
13
1
0
Figure 51. Address Match Logic
P R E L I M I N A R Y
Am79C973/Am79C975
OFLO
CRC
GEN
SEL
12
1
0
CRC
11
RBADR[15:0]
compared with PADR[7:0], with PADR[0] being the
least significant bit of the byte. The second ISO 8802-3
(IEEE/ANSI 802.3) byte is compared with PADR[15:8],
again from the least significant bit to the most signifi-
cant bit, and so on. The sixth byte is compared with
PADR[47:40], the least significant bit being PADR[40].
Mode
The mode register field of the initialization block is cop-
ied into CSR15 and interpreted according to the de-
scription of CSR15.
receive descriptors look like Table 59 (CRDA = Current
Receive Descriptor Address).
When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the
software structures are defined to be 32 bits wide, and
receive descriptors look like Table 60 (CRDA = Current
Receive Descriptor Address).
31
32-Bit Resultant CRC
BUFF
10
26
64
6
63
STP
MUX
Address Filter
9
(LADRF)
Logical
MCNT
BCNT
0
ENP
8
0
Match
RBADR[23:16]
7-0
21510B-56
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